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Re: [PATCH v1 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp t


From: Bin Meng
Subject: Re: [PATCH v1 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
Date: Tue, 1 Jun 2021 21:10:14 +0800

On Mon, May 31, 2021 at 12:33 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>

Please write some commit message here

> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  include/hw/riscv/opentitan.h |  5 ++++-
>  hw/riscv/opentitan.c         | 14 +++++++++++---
>  2 files changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index aab9bc9245..86cceef698 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -22,6 +22,7 @@
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/intc/ibex_plic.h"
>  #include "hw/char/ibex_uart.h"
> +#include "hw/timer/ibex_timer.h"
>  #include "qom/object.h"
>
>  #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
> @@ -35,6 +36,7 @@ struct LowRISCIbexSoCState {
>      RISCVHartArrayState cpus;
>      IbexPlicState plic;
>      IbexUartState uart;
> +    IbexTimerState timer;
>
>      MemoryRegion flash_mem;
>      MemoryRegion rom;
> @@ -57,7 +59,7 @@ enum {
>      IBEX_DEV_SPI,
>      IBEX_DEV_I2C,
>      IBEX_DEV_PATTGEN,
> -    IBEX_DEV_RV_TIMER,
> +    IBEX_DEV_TIMER,
>      IBEX_DEV_SENSOR_CTRL,
>      IBEX_DEV_OTP_CTRL,
>      IBEX_DEV_PWRMGR,
> @@ -82,6 +84,7 @@ enum {
>  };
>
>  enum {
> +    IBEX_TIMER_TIMEREXPIRED0_0 = 125,

So this timer is connected to PLIC, instead of a dedicated exception
code in the *cause CSR?

>      IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
>      IBEX_UART0_RX_TIMEOUT_IRQ = 7,
>      IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 7545dcda9c..c5a7e3bacb 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -36,7 +36,7 @@ static const MemMapEntry ibex_memmap[] = {
>      [IBEX_DEV_SPI] =            {  0x40050000,  0x1000  },
>      [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
>      [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
> -    [IBEX_DEV_RV_TIMER] =       {  0x40100000,  0x1000  },
> +    [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
>      [IBEX_DEV_SENSOR_CTRL] =    {  0x40110000,  0x1000  },
>      [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
>      [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
> @@ -106,6 +106,8 @@ static void lowrisc_ibex_soc_init(Object *obj)
>      object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
>
>      object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
> +
> +    object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
>  }
>
>  static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> @@ -159,6 +161,14 @@ static void lowrisc_ibex_soc_realize(DeviceState 
> *dev_soc, Error **errp)
>                         3, qdev_get_gpio_in(DEVICE(&s->plic),
>                         IBEX_UART0_RX_OVERFLOW_IRQ));
>
> +    if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
> +        return;
> +    }
> +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, 
> memmap[IBEX_DEV_TIMER].base);
> +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
> +                       0, qdev_get_gpio_in(DEVICE(&s->plic),
> +                       IBEX_TIMER_TIMEREXPIRED0_0));
> +
>      create_unimplemented_device("riscv.lowrisc.ibex.gpio",
>          memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.spi",
> @@ -167,8 +177,6 @@ static void lowrisc_ibex_soc_realize(DeviceState 
> *dev_soc, Error **errp)
>          memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
>          memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
> -    create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
> -        memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
>          memmap[IBEX_DEV_SENSOR_CTRL].base, 
> memmap[IBEX_DEV_SENSOR_CTRL].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",

Regards,
Bin



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