Re: [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer

[Alistair Francis]

On Fri, Jun 11, 2021 at 9:52 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> On 11/06/21 01:01, Alistair Francis wrote:
> > On Wed, Jun 9, 2021 at 5:57 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
> >>
> >> On 09/06/21 01:48, Alistair Francis wrote:
> >>> Add support for the Ibex timer. This is used with the RISC-V
> >>> mtime/mtimecmp similar to the SiFive CLINT.
> >>>
> >>> We currently don't support changing the prescale or the timervalue.
> >>>
> >>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> >>
> >> Any chance this could have a qtest?  It would also be nice if the CPU
> >
> > Yep, do you have a good example of what the qtest should look like?
>
> Without having access to the IRQ line it's a bit hard to write it, but
> the qtests for various real-time clocks are probably the closest.
>
> >> had qemu_irqs for MEIP/MTIP/SEIP (possibly MSIP too but that one is
> >> bidirectional), so that instead of riscv_cpu_update_mip you can just
> >> connect to a GPIO pin of the CPU and do qemu_set_irq.  It could also be
> >> used by the qtests via irq_intercept_in.
> >
> > Yeah the riscv_cpu_update_mip() is not ideal. As it is what we
> > currently also use for the CLINT I don't want to fix it up here. In
> > the future I'll work on changing riscv_cpu_update_mip in all the
> > RISC-V timers to use GPIO lines instead.
>
> If you add GPIO output pins to the CPU, the devices can be converted
> away from riscv_cpu_update_mip one by one.

I've added this conversion to my TODO list and hopefully soon I'll be
able to remove riscv_cpu_update_mip(), but I don't want to block this
series or the ACLINT one on that.

Then I can look at qtests.

Alistair

>
> Paolo
>