Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg

[Jose Martins]

> > +static const target_ulong vs_delegable_excps = delegable_excps &
> > +    ~((1ULL << (RISCV_EXCP_S_ECALL)) |
>
> > +    (1ULL << (RISCV_EXCP_VS_ECALL)) |
> > +    (1ULL << (RISCV_EXCP_M_ECALL)) |
>
> These two are both read only 0, shouldn't they not be included in this list?
>
> >  static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
> >  {
> > -    env->hedeleg = val;
> > +    env->hedeleg = val & vs_delegable_excps;
>
> Because we then allow a write to occur here.

Note that the list is being bitwise negated, so both of these are
actually not writable (ie read-only 0). There is still the question
regarding the VS_ECALL (exception 10) bit raised by Zhiwei, since
table 5.2 in the spec does not explicitly classify it. However, I
believe it is safe to assume that exception 10 is non-delegable.

José