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From: | Richard Henderson |
Subject: | Re: [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines |
Date: | Fri, 9 Jul 2021 08:20:52 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 |
On 7/8/21 8:30 PM, Alistair Francis wrote:
Expose the 12 interrupt pending bits in MIP as GPIO lines. Signed-off-by: Alistair Francis<alistair.francis@wdc.com> --- target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
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