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[RFC PATCH 01/13] target/riscv: Add UXL to tb flags
From: |
LIU Zhiwei |
Subject: |
[RFC PATCH 01/13] target/riscv: Add UXL to tb flags |
Date: |
Thu, 5 Aug 2021 10:53:00 +0800 |
For 32-bit applications run on 64-bit cpu, it may share some code
with other 64-bit applictions. Thus we should distinguish the translated
cache of the share code with a tb flag.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 15 +++++++++++++++
target/riscv/translate.c | 3 +++
2 files changed, 18 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bf1c899c00..2b3ba21a78 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -394,9 +394,20 @@ FIELD(TB_FLAGS, SEW, 5, 3)
FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)
+FIELD(TB_FLAGS, UXL, 10, 2)
bool riscv_cpu_is_32bit(CPURISCVState *env);
+static inline bool riscv_cpu_is_uxl32(CPURISCVState *env)
+{
+#ifndef CONFIG_USER_ONLY
+ return (get_field(env->mstatus, MSTATUS64_UXL) == 1) &&
+ !riscv_cpu_is_32bit(env) &&
+ (env->priv == PRV_U);
+#endif
+ return false;
+}
+
/*
* A simplification for VLMAX
* = (1 << LMUL) * VLEN / (8 * (1 << SEW))
@@ -451,6 +462,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState
*env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
}
+ if (riscv_cpu_is_uxl32(env)) {
+ flags = FIELD_DP32(flags, TB_FLAGS, UXL,
+ get_field(env->mstatus, MSTATUS64_UXL));
+ }
#endif
*pflags = flags;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 076f28b9c1..ac4a545da8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -67,6 +67,8 @@ typedef struct DisasContext {
CPUState *cs;
TCGv zero;
TCGv sink;
+ /* UXLEN is 32 bit for 64-bit CPU */
+ bool uxl32;
} DisasContext;
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -912,6 +914,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
ctx->cs = cs;
+ ctx->uxl32 = FIELD_EX32(tb_flags, TB_FLAGS, UXL) == 1;
}
static void riscv_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
--
2.17.1
- [RFC PATCH 00/13] Support UXL field in mstatus, LIU Zhiwei, 2021/08/04
- [RFC PATCH 01/13] target/riscv: Add UXL to tb flags,
LIU Zhiwei <=
- [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, LIU Zhiwei, 2021/08/04
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, Richard Henderson, 2021/08/05
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, LIU Zhiwei, 2021/08/08
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, Richard Henderson, 2021/08/09
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, LIU Zhiwei, 2021/08/11
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, Richard Henderson, 2021/08/11
- Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions, LIU Zhiwei, 2021/08/11