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[RFC PATCH 11/13] target/riscv: Fix srow
From: |
LIU Zhiwei |
Subject: |
[RFC PATCH 11/13] target/riscv: Fix srow |
Date: |
Thu, 5 Aug 2021 10:53:10 +0800 |
Always fill MSB 32 bits with 1s in source register before calling
gen_sro. Otherwise it may not only shift in 1s.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
target/riscv/translate.c | 7 +++++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 58921f3224..0bae0a2bbf 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -339,14 +339,14 @@ static bool trans_srow(DisasContext *ctx, arg_srow *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_shiftw(ctx, a, gen_sro);
+ return gen_shiftw(ctx, a, gen_srow);
}
static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_shiftiw(ctx, a, gen_sro);
+ return gen_shiftiw(ctx, a, gen_srow);
}
static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 160a2df629..5ee0feac4b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -669,6 +669,13 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_not_tl(ret, ret);
}
+static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv ones = tcg_constant_tl(UINT32_MAX);
+ tcg_gen_deposit_tl(arg1, arg1, ones, 32, 32);
+ gen_sro(ret, arg1, arg2);
+}
+
static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
{
TCGv dest = gpr_dst(ctx, a->rd);
--
2.17.1
- [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction, (continued)
- [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction, LIU Zhiwei, 2021/08/04
- [RFC PATCH 06/13] target/riscv: Fix div instructions, LIU Zhiwei, 2021/08/04
- [RFC PATCH 07/13] target/riscv: Support UXL32 for RVM, LIU Zhiwei, 2021/08/04
- [RFC PATCH 08/13] target/riscv: Support UXL32 for vector instructions, LIU Zhiwei, 2021/08/04
- [RFC PATCH 09/13] target/riscv: Support UXL32 for atomic instructions, LIU Zhiwei, 2021/08/04
- [RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions, LIU Zhiwei, 2021/08/04
- [RFC PATCH 11/13] target/riscv: Fix srow,
LIU Zhiwei <=
- [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB, LIU Zhiwei, 2021/08/04
- [RFC PATCH 13/13] target/riscv: Changing the width of U-mode CSR, LIU Zhiwei, 2021/08/04
- Re: [RFC PATCH 00/13] Support UXL field in mstatus, Alistair Francis, 2021/08/05