Re: [RFC PATCH 03/13] target/riscv: Support UXL32 on 64-bit cpu for load/store

[Richard Henderson]

On 8/4/21 4:53 PM, LIU Zhiwei wrote:
> Get the LSB 32 bits and zero-extend as the base address.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
>   target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc 
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index ea41d1de2d..6823a6b3e0 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -163,7 +163,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
>   static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
>   {
>       TCGv dest = gpr_dst(ctx, a->rd);
> -    TCGv addr = gpr_src(ctx, a->rs1);
> +    TCGv addr = gpr_src_u(ctx, a->rs1);
>       TCGv temp = NULL;
>   
>       if (a->imm) {
> @@ -207,7 +207,7 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
>   
>   static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
>   {
> -    TCGv addr = gpr_src(ctx, a->rs1);
> +    TCGv addr = gpr_src_u(ctx, a->rs1);
>       TCGv data = gpr_src(ctx, a->rs2);
>       TCGv temp = NULL;

This is incorrect.  The zero-extension should happen after the addition of the immediate 
offset.

r~