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Re: [PATCH v2 15/21] target/riscv: Reorg csr instructions


From: Bin Meng
Subject: Re: [PATCH v2 15/21] target/riscv: Reorg csr instructions
Date: Thu, 19 Aug 2021 15:08:12 +0800

On Wed, Aug 18, 2021 at 5:27 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Introduce csrr and csrw helpers, for read-only and write-only insns.
>
> Note that we do not properly implement this in riscv_csrrw, in that
> we cannot distinguish true read-only (rs1 == 0) from any other zero
> write_mask another source register -- this should still raise an
> exception for read-only registers.
>
> Only issue gen_io_start for CF_USE_ICOUNT.
> Use ctx->zero for csrrc.
> Use get_gpr and dest_gpr.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/helper.h                   |   6 +-
>  target/riscv/op_helper.c                |  18 +--
>  target/riscv/insn_trans/trans_rvi.c.inc | 172 +++++++++++++++++-------
>  3 files changed, 131 insertions(+), 65 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>



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