Re: [PATCH] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v

[Alistair Francis]

On Thu, Oct 7, 2021 at 6:18 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> oprsz and maxsz are passed with the same value in commit: eee2d61e202.
> However, vmv.v.v was missed in that commit and should pass the same
> value as well in its tcg_gen_gvec_2_ptr() call.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index fa451938f1e..f730bd68d18 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1619,7 +1619,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v 
> *a)
>              tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>
>              tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
> -                               cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
> +                               cpu_env, s->vlen / 8, s->vlen / 8, data,
> +                               fns[s->sew]);
>              gen_set_label(over);
>          }
>          return true;
> --
> 2.25.1
>
>