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Re: [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction |
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Date: |
Mon, 18 Oct 2021 15:49:28 +1000 |
On Fri, Oct 15, 2021 at 6:25 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 2 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 10 ++++++++--
> 2 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index d139c0aade7..3ac5162aeb7 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -632,7 +632,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111
> @r2_vm
> vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
> vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
> vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
> -viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
> +viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
> vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
> vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
> vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 538a32a605a..3751496676f 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2756,12 +2756,18 @@ GEN_M_TRANS(vmsbf_m)
> GEN_M_TRANS(vmsif_m)
> GEN_M_TRANS(vmsof_m)
>
> -/* Vector Iota Instruction */
> +/*
> + * Vector Iota Instruction
> + *
> + * 1. The destination register cannot overlap the source register.
> + * 2. If masked, cannot overlap the mask register ('v0').
> + * 3. An illegal instruction exception is raised if vstart is non-zero.
> + */
> static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
> {
> if (require_rvv(s) &&
> vext_check_isa_ill(s) &&
> - require_noover(a->rd, s->lmul, a->rs2, 0) &&
> + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
> require_vm(a->vm, a->rd) &&
> require_align(a->rd, s->lmul)) {
> uint32_t data = 0;
> --
> 2.25.1
>
>
- [PATCH v8 26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, (continued)
- [PATCH v8 26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2021/10/15
- [PATCH v8 28/78] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2021/10/15
- [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction, frank . chang, 2021/10/15
- [PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2021/10/15
- [PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/10/15
- [PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/10/15
- [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/10/15
- Re: [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction,
Alistair Francis <=
- [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/10/15
- [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/10/15
- [PATCH v8 35/78] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/10/15
- [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/10/15
- [PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2021/10/15
- [PATCH v8 39/78] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/10/15