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Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh |
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Date: |
Mon, 18 Oct 2021 16:01:24 +1000 |
On Fri, Oct 15, 2021 at 5:50 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
> commit: c445593, but other TB_FLAGS bits for rvv and rvh were
> not shift as well so these bits may overlap with each other when
> rvv is enabled.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Thanks!
Applied to this patch to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.h | 14 +++++++-------
> target/riscv/translate.c | 2 +-
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d70f63ddfe6..d63a08b6e4c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -380,7 +380,6 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState
> *env,
> target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
> void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>
> -#define TB_FLAGS_MMU_MASK 7
> #define TB_FLAGS_PRIV_MMU_MASK 3
> #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> @@ -389,13 +388,14 @@ typedef CPURISCVState CPUArchState;
> typedef RISCVCPU ArchCPU;
> #include "exec/cpu-all.h"
>
> -FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
> -FIELD(TB_FLAGS, LMUL, 3, 2)
> -FIELD(TB_FLAGS, SEW, 5, 3)
> -FIELD(TB_FLAGS, VILL, 8, 1)
> +FIELD(TB_FLAGS, MEM_IDX, 0, 3)
> +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
> +FIELD(TB_FLAGS, LMUL, 4, 2)
> +FIELD(TB_FLAGS, SEW, 6, 3)
> +FIELD(TB_FLAGS, VILL, 9, 1)
> /* Is a Hypervisor instruction load/store allowed? */
> -FIELD(TB_FLAGS, HLSX, 9, 1)
> -FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
> +FIELD(TB_FLAGS, HLSX, 10, 1)
> +FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
>
> bool riscv_cpu_is_32bit(CPURISCVState *env);
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index f23bc919c08..a7a66cf9db1 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -544,7 +544,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
> *dcbase, CPUState *cs)
> uint32_t tb_flags = ctx->base.tb->flags;
>
> ctx->pc_succ_insn = ctx->base.pc_first;
> - ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
> + ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
> ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
> ctx->priv_ver = env->priv_ver;
> #if !defined(CONFIG_USER_ONLY)
> --
> 2.25.1
>
>
- [PATCH v8 00/78] support vector extension v1.0, frank . chang, 2021/10/15
- [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, frank . chang, 2021/10/15
- [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/10/15
- [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/10/15
- [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/10/15
- [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/10/15
- [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/10/15
- [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/10/15
- [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/10/15
- [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/10/15
- [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/10/15
- [PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/10/15