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Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and Mac
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From: |
Bin Meng |
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Subject: |
Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id |
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Date: |
Tue, 19 Oct 2021 00:00:26 +0800 |
Hi Philippe,
On Mon, Oct 18, 2021 at 11:51 PM Philippe Mathieu-Daudé
<philmd@redhat.com> wrote:
>
> Hi Bin, is there a cover letter?
Sorry, I did not include a cover letter. I will need to remember this
next time :)
>
> Series:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
Thanks for the review!
Regards,
Bin
- Re: [PATCH 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id, (continued)
- [PATCH 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Philippe Mathieu-Daudé, 2021/10/18
- Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id,
Bin Meng <=
- Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Igor Mammedov, 2021/10/19