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Re: [PATCH v3 04/21] target/riscv: additional macros to check instructio
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From: |
Frédéric Pétrot |
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Subject: |
Re: [PATCH v3 04/21] target/riscv: additional macros to check instruction support |
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Date: |
Thu, 21 Oct 2021 18:22:33 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 |
Le 20/10/2021 à 16:08, Richard Henderson a écrit :
> On 10/19/21 2:47 AM, Frédéric Pétrot wrote:
>> +
>> +#define REQUIRE_64_OR_128BIT(ctx) do { \
>> + if (get_xl(ctx) == MXL_RV32) { \
>> + return false; \
>> + } \
>> +} while (0)
>
> So... you've left REQUIRE_64BIT accepting RV128, so that means that your
> current
> REQUIRE_64_OR_128BIT is redundant. Is that intentional?
>
> It does seem like all places that accept RV128 should accept RV64, but perhaps
> that's just your "limited" caveat in the cover letter.
My bad, indeed there is no instruction only required by RV64. "Limited" was
related to the minimal support of the priviledge spec.
> You don't use REQUIRE_32_OR_64BIT at all. Remove it?
It's a bug : some compressed insns are only RV32/RV64 (this is linked to
the other bug in the order in which the insns stand in the insn16.decode
file that you pointed out).
Frédéric
>
>
> r~
--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
+---------------------------------------------------------------------------+
- [PATCH v3 00/21] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2021/10/19
- [PATCH v3 02/21] memory: add a few defines for octo (128-bit) values, Frédéric Pétrot, 2021/10/19
- [PATCH v3 04/21] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/19
- [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/19
- [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/19
- [PATCH v3 09/21] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/19
- [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/19
- [PATCH v3 01/21] memory: change define name for consistency, Frédéric Pétrot, 2021/10/19