Re: [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM ex

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Re: [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM ex

From:	Richard Henderson
Subject:	Re: [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
Date:	Mon, 25 Oct 2021 11:46:55 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/25/21 10:36 AM, Alexey Baturo wrote:

+    /* User Pointer Masking */
+    [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,    write_umte  
  },
+    [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask, 
write_upmmask },
+    [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase, 
write_upmbase },
+    /* Machine Pointer Masking */
+    [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,    write_mmte  
  },
+    [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask, 
write_mpmmask },
+    [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase, 
write_mpmbase },
+    /* Supervisor Pointer Masking */
+    [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,    write_smte  
  },
+    [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask, 
write_spmmask },
+    [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase, 
write_spmbase },


Surely the S-mode and U-mode csrs surely also depend on RVS and RVU 
respectively?


r~

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[PATCH v17 0/8] RISC-V Pointer Masking implementation, Alexey Baturo, 2021/10/25
- [PATCH v17 7/8] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2021/10/25
- [PATCH v17 1/8] target/riscv: Add J-extension into RISC-V, Alexey Baturo, 2021/10/25
- [PATCH v17 4/8] target/riscv: Add J extension state description, Alexey Baturo, 2021/10/25
- [PATCH v17 2/8] target/riscv: Add CSR defines for RISC-V PM extension, Alexey Baturo, 2021/10/25
- [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Alexey Baturo, 2021/10/25
  - Re: [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Richard Henderson <=
- [PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs, Alexey Baturo, 2021/10/25
  - Re: [PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs, Alistair Francis, 2021/10/25
- [PATCH v17 6/8] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2021/10/25
- [PATCH v17 8/8] target/riscv: Allow experimental J-ext to be turned on, Alexey Baturo, 2021/10/25

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