Re: [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol

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Re: [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol

From:	Richard Henderson
Subject:	Re: [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol
Date:	Mon, 1 Nov 2021 06:55:57 -0400
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 11/1/21 6:01 AM, LIU Zhiwei wrote:

-            ((1 << s->sew) <= sizeof(target_ulong)) &&
+            ((1 << s->sew) <= (get_olen(s) / 8)) &&


XLEN not OLEN.

But this will also clash with rv128, since we still won't have 128-bit atomics. So Ithink you need to be more reserved in this change:


    /* TODO: RV128 could allow 128-bit atomics */
    (get_xl(s) == MXL_RV32 ? 4 : 8)


r~

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[PATCH 09/13] target/riscv: Adjust vector address with ol, (continued)
- [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 2021/11/01
  - Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, Richard Henderson, 2021/11/01
    - Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 2021/11/08
    - Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, Richard Henderson, 2021/11/09
    - Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 2021/11/09
    - Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, Richard Henderson, 2021/11/09
    - Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 2021/11/09
    - Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 2021/11/09
    - Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, Richard Henderson, 2021/11/09
- [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol, LIU Zhiwei, 2021/11/01
  - Re: [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol, Richard Henderson <=
- [PATCH 06/13] target/riscv: Adjust vsetvl according to ol, LIU Zhiwei, 2021/11/01
  - Re: [PATCH 06/13] target/riscv: Adjust vsetvl according to ol, Richard Henderson, 2021/11/01
- [PATCH 13/13] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/01
  - Re: [PATCH 13/13] target/riscv: Enable uxl field write, Richard Henderson, 2021/11/01
    - Re: [PATCH 13/13] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/08
    - Re: [PATCH 13/13] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/09
- [PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol, LIU Zhiwei, 2021/11/01
  - Re: [PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol, Richard Henderson, 2021/11/01
    - Re: [PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol, LIU Zhiwei, 2021/11/08
- [PATCH 08/13] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/01

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