Re: [PATCH v5 01/18] exec/memop: Adding signedness to quad definitions

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Re: [PATCH v5 01/18] exec/memop: Adding signedness to quad definitions

From:	Richard Henderson
Subject:	Re: [PATCH v5 01/18] exec/memop: Adding signedness to quad definitions
Date:	Sun, 14 Nov 2021 13:49:25 +0100
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0

On 11/12/21 3:58 PM, Frédéric Pétrot wrote:

Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.

Signed-off-by: Frédéric Pétrot<frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
---


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

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[PATCH v5 00/18] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2021/11/12
- [PATCH v5 03/18] qemu/int128: addition of div/rem 128-bit operations, Frédéric Pétrot, 2021/11/12
  - Re: [PATCH v5 03/18] qemu/int128: addition of div/rem 128-bit operations, Alistair Francis, 2021/11/23
- [PATCH v5 01/18] exec/memop: Adding signedness to quad definitions, Frédéric Pétrot, 2021/11/12
  - Re: [PATCH v5 01/18] exec/memop: Adding signedness to quad definitions, Richard Henderson <=
- [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines, Frédéric Pétrot, 2021/11/12
  - Re: [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines, Richard Henderson, 2021/11/15
  - Re: [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines, Alistair Francis, 2021/11/22
  - Re: [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines, Philippe Mathieu-Daudé, 2021/11/24
- [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/11/12
  - Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Alistair Francis, 2021/11/23
    - Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/11/23
    - Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Alistair Francis, 2021/11/23
- [PATCH v5 04/18] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/11/12
  - Re: [PATCH v5 04/18] target/riscv: additional macros to check instruction support, Alistair Francis, 2021/11/23

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