qemu-riscv
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v2 6/7] target/riscv: cpu: Enable native debug feature on vir


From: Alistair Francis
Subject: Re: [PATCH v2 6/7] target/riscv: cpu: Enable native debug feature on virt and sifive_u CPUs
Date: Wed, 17 Nov 2021 10:57:56 +1000

On Sat, Oct 30, 2021 at 11:56 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Turn on native debug feature on virt and sifive_u CPUs.

Is there a reason why it's only these 2 machines? Could this be
enabled by default for all CPUs?

Alistair

>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
>
> ---
>
> Changes in v2:
> - new patch: enable native debug feature on virt and sifive_u CPUs
>
>  target/riscv/cpu.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6f69ef4f50..b4d3c58dea 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -153,6 +153,7 @@ static void rv64_base_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      /* We set this in the realise function */
>      set_misa(env, MXL_RV64, 0);
> +    qdev_prop_set_bit(DEVICE(obj), "debug", true);
>  }
>
>  static void rv64_sifive_u_cpu_init(Object *obj)
> @@ -160,6 +161,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
> +    qdev_prop_set_bit(DEVICE(obj), "debug", true);
>  }
>
>  static void rv64_sifive_e_cpu_init(Object *obj)
> @@ -175,6 +177,7 @@ static void rv32_base_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      /* We set this in the realise function */
>      set_misa(env, MXL_RV32, 0);
> +    qdev_prop_set_bit(DEVICE(obj), "debug", true);
>  }
>
>  static void rv32_sifive_u_cpu_init(Object *obj)
> @@ -182,6 +185,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
> +    qdev_prop_set_bit(DEVICE(obj), "debug", true);
>  }
>
>  static void rv32_sifive_e_cpu_init(Object *obj)
> --
> 2.25.1
>
>



reply via email to

[Prev in Thread] Current Thread [Next in Thread]