[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 20/22] target/riscv: Adjust vector address with mask
From: |
LIU Zhiwei |
Subject: |
[PATCH v5 20/22] target/riscv: Adjust vector address with mask |
Date: |
Thu, 25 Nov 2021 15:39:49 +0800 |
The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e3ac70da01..c3976cc3d4 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -116,6 +116,11 @@ static inline uint32_t vext_maxsz(uint32_t desc)
return simd_maxsz(desc) << vext_lmul(desc);
}
+static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
+{
+ return (addr & env->cur_pmmask) | env->cur_pmbase;
+}
+
/*
* This function checks watchpoint before real load operation.
*
@@ -133,12 +138,12 @@ static void probe_pages(CPURISCVState *env, target_ulong
addr,
target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
target_ulong curlen = MIN(pagelen, len);
- probe_access(env, addr, curlen, access_type,
+ probe_access(env, adjust_addr(env, addr), curlen, access_type,
cpu_mmu_index(env, false), ra);
if (len > curlen) {
addr += curlen;
curlen = len - curlen;
- probe_access(env, addr, curlen, access_type,
+ probe_access(env, adjust_addr(env, addr), curlen, access_type,
cpu_mmu_index(env, false), ra);
}
}
@@ -299,7 +304,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
}
while (k < nf) {
target_ulong addr = base + stride * i + k * msz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
k++;
}
}
@@ -392,7 +397,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState
*env, uint32_t desc,
k = 0;
while (k < nf) {
target_ulong addr = base + (i * nf + k) * msz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
k++;
}
}
@@ -529,7 +534,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
}
while (k < nf) {
abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
k++;
}
}
@@ -619,7 +624,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, mlen, i)) {
continue;
}
- addr = base + nf * i * msz;
+ addr = adjust_addr(env, base + nf * i * msz);
if (i == 0) {
probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
} else {
@@ -646,7 +651,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
break;
}
remain -= offset;
- addr += offset;
+ addr = adjust_addr(env, addr + offset);
}
}
}
@@ -662,7 +667,7 @@ ProbeSuccess:
}
while (k < nf) {
target_ulong addr = base + (i * nf + k) * msz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
k++;
}
}
@@ -801,7 +806,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
continue;
}
addr = get_index_addr(base, i, vs2);
- noatomic_op(vs3, addr, wd, i, env, ra);
+ noatomic_op(vs3, adjust_addr(env, addr), wd, i, env, ra);
}
clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz);
}
--
2.25.1
- Re: [PATCH v5 10/22] target/riscv: Create current pm fields in env, (continued)
- [PATCH v5 11/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2021/11/25
- [PATCH v5 12/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 13/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2021/11/25
- [PATCH v5 14/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/25
- [PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 2021/11/25
- [PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2021/11/25
- [PATCH v5 18/22] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 19/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/25
- [PATCH v5 20/22] target/riscv: Adjust vector address with mask,
LIU Zhiwei <=
- [PATCH v5 21/22] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 22/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/25