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Re: [PATCH v10 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstat
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v10 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty |
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Date: |
Mon, 29 Nov 2021 13:16:44 +1000 |
On Mon, Nov 29, 2021 at 1:07 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9b5bd5d7b49..bb500afdeb5 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -502,6 +502,7 @@ static RISCVException read_mhartid(CPURISCVState *env,
> int csrno,
> static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
> {
> if ((status & MSTATUS_FS) == MSTATUS_FS ||
> + (status & MSTATUS_VS) == MSTATUS_VS ||
> (status & MSTATUS_XS) == MSTATUS_XS) {
> switch (xl) {
> case MXL_RV32:
> --
> 2.25.1
>
>
- [PATCH v10 00/77] support vector extension v1.0, frank . chang, 2021/11/28
- [PATCH v10 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/11/28
- [PATCH v10 02/77] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/11/28
- [PATCH v10 03/77] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/11/28
- [PATCH v10 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, frank . chang, 2021/11/28
- Re: [PATCH v10 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty,
Alistair Francis <=
- [PATCH v10 05/77] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/11/28
- [PATCH v10 07/77] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/11/28
- [PATCH v10 09/77] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/11/28
- [PATCH v10 08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/11/28
- [PATCH v10 10/77] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/11/28
- [PATCH v10 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/11/28
- [PATCH v10 12/77] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/11/28
- [PATCH v10 14/77] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/11/28
- [PATCH v10 15/77] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/11/28
- [PATCH v10 16/77] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2021/11/28