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Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support
From: |
Alistair Francis |
Subject: |
Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution |
Date: |
Fri, 7 Jan 2022 07:24:05 +1000 |
On Fri, Jan 7, 2022 at 7:04 AM Frédéric Pétrot
<frederic.petrot@univ-grenoble-alpes.fr> wrote:
>
> This patch adds the support of the '-cpu rv128' option to
> qemu-system-riscv64 so that we can indicate that we want to run rv128
> executables.
> Still, there is no support for 128-bit insns at that stage so qemu fails
> miserably (as expected) if launched with this option.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/disas/dis-asm.h | 1 +
> target/riscv/cpu.h | 1 +
> disas/riscv.c | 5 +++++
> target/riscv/cpu.c | 20 ++++++++++++++++++++
> target/riscv/gdbstub.c | 5 +++++
> 5 files changed, 32 insertions(+)
>
> diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
> index 08e1beec85..102a1e7f50 100644
> --- a/include/disas/dis-asm.h
> +++ b/include/disas/dis-asm.h
> @@ -459,6 +459,7 @@ int print_insn_nios2(bfd_vma, disassemble_info*);
> int print_insn_xtensa (bfd_vma, disassemble_info*);
> int print_insn_riscv32 (bfd_vma, disassemble_info*);
> int print_insn_riscv64 (bfd_vma, disassemble_info*);
> +int print_insn_riscv128 (bfd_vma, disassemble_info*);
> int print_insn_rx(bfd_vma, disassemble_info *);
> int print_insn_hexagon(bfd_vma, disassemble_info *);
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index fa5d238530..efe481f5fb 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -38,6 +38,7 @@
> #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> +#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("rv128")
As this series only adds partial support for 128-bit support, I think
we should probably change this to "x-rv128". That way we indicate to
users that it is experimental. That allows us more flexibility in the
future to have breaking changes and will hopefully avoid confusion
about the current state. What do you think? I can just make the change
when I apply the patches.
Alistair
- [PATCH v8 00/18] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2022/01/06
- [PATCH v8 02/18] exec/memop: Adding signed quad and octo defines, Frédéric Pétrot, 2022/01/06
- [PATCH v8 01/18] exec/memop: Adding signedness to quad definitions, Frédéric Pétrot, 2022/01/06
- [PATCH v8 04/18] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2022/01/06
- [PATCH v8 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2022/01/06
- [PATCH v8 03/18] qemu/int128: addition of div/rem 128-bit operations, Frédéric Pétrot, 2022/01/06
- [PATCH v8 05/18] target/riscv: separation of bitwise logic and arithmetic helpers, Frédéric Pétrot, 2022/01/06
- [PATCH v8 08/18] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2022/01/06
- [PATCH v8 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2022/01/06
- [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution, Frédéric Pétrot, 2022/01/06
- Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution,
Alistair Francis <=
[PATCH v8 10/18] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2022/01/06
[PATCH v8 15/18] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2022/01/06
[PATCH v8 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2022/01/06
[PATCH v8 11/18] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2022/01/06
[PATCH v8 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2022/01/06
[PATCH v8 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2022/01/06
[PATCH v8 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2022/01/06