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[PATCH v4 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
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From: |
Weiwei Li |
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Subject: |
[PATCH v4 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties |
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Date: |
Thu, 13 Jan 2022 09:49:59 +0800 |
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fc3ec5bca1..d5e772b2b8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -685,6 +685,11 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ DEFINE_PROP_BOOL("Zdinx", RISCVCPU, cfg.ext_zdinx, false),
+ DEFINE_PROP_BOOL("Zfinx", RISCVCPU, cfg.ext_zfinx, false),
+ DEFINE_PROP_BOOL("Zhinx", RISCVCPU, cfg.ext_zhinx, false),
+ DEFINE_PROP_BOOL("Zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
+
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
--
2.17.1
- [PATCH v4 0/6] support subsets of Float-Point in Integer Registers extensions, Weiwei Li, 2022/01/12
- [PATCH v4 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx, Weiwei Li, 2022/01/12
- [PATCH v4 3/6] target/riscv: add support for zfinx, Weiwei Li, 2022/01/12
- [PATCH v4 5/6] target/riscv: add support for zhinx/zhinxmin, Weiwei Li, 2022/01/12
- [PATCH v4 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}, Weiwei Li, 2022/01/12
- [PATCH v4 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties,
Weiwei Li <=
- [PATCH v4 4/6] target/riscv: add support for zdinx, Weiwei Li, 2022/01/12