|
| From: | Weiwei Li |
| Subject: | Re: [PATCH v3 2/3] target/riscv: add support for svinval extension |
| Date: | Fri, 14 Jan 2022 22:35:43 +0800 |
| User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 |
在 2022/1/14 下午10:01, Anup Patel 写道:
On Fri, Jan 14, 2022 at 7:24 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:Thanks for your comments. 在 2022/1/14 下午9:40, Anup Patel 写道: On Fri, Jan 14, 2022 at 7:11 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote: Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++ target/riscv/translate.c | 1 + 5 files changed, 85 insertions(+) create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ff6c86c85b..45ac98e06b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -668,6 +668,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), + DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d3d17cde82..c3d1845ca1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -327,6 +327,7 @@ struct RISCVCPU { bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_svinval; bool ext_svnapot; bool ext_zfh; bool ext_zfhmin; diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 5bbedc254c..7a0351fde2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -809,3 +809,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm + +# *** Svinval Standard Extension *** +sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma +sfence_w_inval 0001100 00000 00000 000 00000 1110011 +sfence_inval_ir 0001100 00001 00000 000 00000 1110011 +hinval_vvma 0011011 ..... ..... 000 00000 1110011 @hfence_vvma s/0011011/0010011/ +hinval_gvma 0111011 ..... ..... 000 00000 1110011 @hfence_gvma s/0111011/0110011/ Sorry. I didn't find the encodings for svinval instructions from the spec. So I get them from spike (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/encoding.h) which are as follows: #define MATCH_HINVAL_VVMA 0x36000073 #define MASK_HINVAL_VVMA 0xfe007fff #define MATCH_HINVAL_GVMA 0x76000073 #define MASK_HINVAL_GVMA 0xfe007fff Are they not the latest encodings?The code in Spike seems to be buggy but that's a separate issue. Refer, page 138 of https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220110-eae4f00/riscv-privileged.pdf Regards, Anup
OK. Thanks a lot. I'll fix this. Regards, Weiwei Li
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc new file mode 100644 index 0000000000..1dde665661 --- /dev/null +++ b/target/riscv/insn_trans/trans_svinval.c.inc @@ -0,0 +1,75 @@ +/* + * RISC-V translation routines for the Svinval Standard Instruction Set. + * + * Copyright (c) 2020-2021 PLCT lab + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#define REQUIRE_SVINVAL(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) { \ + return false; \ + } \ +} while (0) + +static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a) +{ + REQUIRE_SVINVAL(ctx); + /* Do the same as sfence.vma currently */ + REQUIRE_EXT(ctx, RVS); +#ifndef CONFIG_USER_ONLY + gen_helper_tlb_flush(cpu_env); + return true; +#endif + return false; +} + +static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a) +{ + REQUIRE_SVINVAL(ctx); + REQUIRE_EXT(ctx, RVS); + /* Do nothing currently */ + return true; +} + +static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a) +{ + REQUIRE_SVINVAL(ctx); + REQUIRE_EXT(ctx, RVS); + /* Do nothing currently */ + return true; +} + +static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a) +{ + REQUIRE_SVINVAL(ctx); + /* Do the same as hfence.vvma currently */ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + gen_helper_hyp_tlb_flush(cpu_env); + return true; +#endif + return false; +} + +static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a) +{ + REQUIRE_SVINVAL(ctx); + /* Do the same as hfence.gvma currently */ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + gen_helper_hyp_gvma_tlb_flush(cpu_env); + return true; +#endif + return false; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 615048ec87..4e5a9660a4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -838,6 +838,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvb.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_privileged.c.inc" +#include "insn_trans/trans_svinval.c.inc" /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" -- 2.17.1 Apart from the minor mistake above, it looks good to me. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup Regards, Weiwei Li
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