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[PATCH v7 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
From: |
Anup Patel |
Subject: |
[PATCH v7 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs |
Date: |
Mon, 17 Jan 2022 18:58:26 +0530 |
From: Anup Patel <anup.patel@wdc.com>
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
hw/riscv/virt.c | 10 ++++++++++
include/hw/riscv/virt.h | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 73b2be7b60..f9cf7551b4 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -44,6 +44,16 @@
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
#if VIRT_IMSIC_GROUP_MAX_SIZE < \
IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 7898c574af..78f450eb60 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -24,7 +24,7 @@
#include "hw/block/flash.h"
#include "qom/object.h"
-#define VIRT_CPUS_MAX_BITS 3
+#define VIRT_CPUS_MAX_BITS 9
#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
#define VIRT_SOCKETS_MAX_BITS 2
#define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS)
--
2.25.1
- [PATCH v7 16/23] hw/riscv: virt: Use AIA INTC compatible string when available, (continued)
- [PATCH v7 16/23] hw/riscv: virt: Use AIA INTC compatible string when available, Anup Patel, 2022/01/17
- [PATCH v7 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback, Anup Patel, 2022/01/17
- [PATCH v7 07/23] target/riscv: Add defines for AIA CSRs, Anup Patel, 2022/01/17
- [PATCH v7 17/23] target/riscv: Allow users to force enable AIA CSRs in HART, Anup Patel, 2022/01/17
- [PATCH v7 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine, Anup Patel, 2022/01/17
- [PATCH v7 05/23] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2022/01/17
- [PATCH v7 18/23] hw/intc: Add RISC-V AIA APLIC device emulation, Anup Patel, 2022/01/17
- [PATCH v7 22/23] docs/system: riscv: Document AIA options for virt machine, Anup Patel, 2022/01/17
- [PATCH v7 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Anup Patel, 2022/01/17
- [PATCH v7 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs,
Anup Patel <=
- [PATCH v7 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation, Anup Patel, 2022/01/17
- [PATCH v7 06/23] target/riscv: Add AIA cpu feature, Anup Patel, 2022/01/17
- [PATCH v7 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Anup Patel, 2022/01/17