Re: [PATCH 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:41 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Vector single-width floating-point reduction operations for EEW=32 are
> supported for Zve64f extension.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 0aa8b7918f..d7e288b87f 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2935,7 +2935,8 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, 
> reduction_widen_check)
>  static bool freduction_check(DisasContext *s, arg_rmrr *a)
>  {
>      return reduction_check(s, a) &&
> -           require_rvf(s);
> +           require_rvf(s) &&
> +           require_zve64f(s);
>  }
>
>  GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)
> --
> 2.31.1
>
>