Re: [PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:48 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Vector single-width floating-point reduction operations for EEW=32 are
> supported for Zve32f extension.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 1f5a75eca7..c3f4dabf36 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2974,6 +2974,7 @@ static bool freduction_check(DisasContext *s, arg_rmrr 
> *a)
>  {
>      return reduction_check(s, a) &&
>             require_rvf(s) &&
> +           require_zve32f(s) &&
>             require_zve64f(s);
>  }
>
> --
> 2.31.1
>
>