Re: [PATCH v7 3/5] target/riscv: add support for svnapot extension

[Weiwei Li]

在 2022/2/1 下午2:22, Alistair Francis 写道:
> On Fri, Jan 28, 2022 at 6:57 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
> > - add PTE_N bit
> > - add PTE_N bit check for inner PTE
> > - update address translation to support 64KiB continuous region (napot_bits = 4)
> >
> > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> > Reviewed-by: Anup Patel <anup@brainfault.org>
> > ---
> >   target/riscv/cpu.c        |  2 ++
> >   target/riscv/cpu_bits.h   |  1 +
> >   target/riscv/cpu_helper.c | 17 ++++++++++++++---
> >   3 files changed, 17 insertions(+), 3 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 1cb0436187..8752fa1544 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -729,6 +729,8 @@ static Property riscv_cpu_properties[] = {
> >       DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> >       DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> >
> > +    DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> > +
> >       DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> >       DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> >       DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 6ea3944423..f6ff1c5012 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -489,6 +489,7 @@ typedef enum {
> >   #define PTE_A               0x040 /* Accessed */
> >   #define PTE_D               0x080 /* Dirty */
> >   #define PTE_SOFT            0x300 /* Reserved for Software */
> > +#define PTE_N               0x8000000000000000 /* NAPOT translation */
> This should be 0x8000000000000000ULL to avoid casting
OK. I'll fix it.
> >   /* Page table PPN shift amount */
> >   #define PTE_PPN_SHIFT       10
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index b820166dc5..6262d157e2 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -641,7 +641,7 @@ restart:
> >               return TRANSLATE_FAIL;
> >           } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> >               /* Inner PTE, continue walking */
> > -            if (pte & (PTE_D | PTE_A | PTE_U)) {
> > +            if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) {
> >                   return TRANSLATE_FAIL;
> >               }
> >               base = ppn << PGSHIFT;
> > @@ -717,8 +717,19 @@ restart:
> >               /* for superpage mappings, make a fake leaf PTE for the TLB's
> >                  benefit. */
> >               target_ulong vpn = addr >> PGSHIFT;
> > -            *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
> > -                        (addr & ~TARGET_PAGE_MASK);
> > +
> > +            int napot_bits = 0;
> > +            if (cpu->cfg.ext_svnapot && (pte & (target_ulong)PTE_N)) {
> > +                napot_bits = ctzl(ppn) + 1;
> > +                if ((i != (levels - 1)) || (napot_bits != 4)) {
> > +                    return TRANSLATE_FAIL;
> > +                }
> > +            }
> > +
> > +            *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
> It might be clearer to create the mask as a variable, there are a lot
> of brackets here :)
OK.
> Alistair
>
> > +                          (vpn & (((target_ulong)1 << napot_bits) - 1)) |
> > +                          (vpn & (((target_ulong)1 << ptshift) - 1))
> > +                        ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
> >
> >               /* set permissions on the TLB entry */
> >               if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
> > --
> > 2.17.1