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[PATCH v6 02/12] target/riscv: Implement PMU CSR predicate function for
From: |
Atish Patra |
Subject: |
[PATCH v6 02/12] target/riscv: Implement PMU CSR predicate function for S-mode |
Date: |
Thu, 3 Mar 2022 15:54:30 -0800 |
From: Atish Patra <atish.patra@wdc.com>
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6102d5e7e24f..cb4366b30095 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -76,6 +76,57 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ if (env->priv == PRV_S) {
+ switch (csrno) {
+ case CSR_CYCLE:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIME:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRET:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+ ctr_index = csrno - CSR_CYCLE;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ if (riscv_cpu_is_32bit(env)) {
+ switch (csrno) {
+ case CSR_CYCLEH:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIMEH:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRETH:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+ ctr_index = csrno - CSR_CYCLEH;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ }
+ }
+
if (riscv_cpu_virt_enabled(env)) {
switch (csrno) {
case CSR_CYCLE:
--
2.30.2
- [PATCH v6 00/12] Improve PMU support, Atish Patra, 2022/03/03
- [PATCH v6 01/12] target/riscv: Fix PMU CSR predicate function, Atish Patra, 2022/03/03
- [PATCH v6 03/12] target/riscv: pmu: Rename the counters extension to pmu, Atish Patra, 2022/03/03
- [PATCH v6 02/12] target/riscv: Implement PMU CSR predicate function for S-mode,
Atish Patra <=
- [PATCH v6 04/12] target/riscv: pmu: Make number of counters configurable, Atish Patra, 2022/03/03
- [PATCH v6 05/12] target/riscv: Implement mcountinhibit CSR, Atish Patra, 2022/03/03
- [PATCH v6 06/12] target/riscv: Add support for hpmcounters/hpmevents, Atish Patra, 2022/03/03
- [PATCH v6 07/12] target/riscv: Support mcycle/minstret write operation, Atish Patra, 2022/03/03
- [PATCH v6 08/12] target/riscv: Add sscofpmf extension support, Atish Patra, 2022/03/03
- [PATCH v6 10/12] target/riscv: Add few cache related PMU events, Atish Patra, 2022/03/03