Re: [PATCH v4 14/14] hw: set user_creatable on opentitan/sifive_e devices

[Philippe Mathieu-Daudé]

On 23/2/22 10:07, Damien Hedde wrote:
> The devices are:
> + ibex-timer
> + ibex-uart
> + riscv.aclint.swi
> + riscv.aclint.mtimer
> + riscv.hart_array
> + riscv.sifive.e.prci
> + riscv.sifive.plic
> + riscv.sifive.uart
> + sifive_soc.gpio
> + unimplemented-device
>
> These devices are clean regarding error handling in realize.
>
> They are all sysbus devices, so setting user-creatable will only
> enable cold-plugging them on machine having explicitely allowed them
> (only _none_ machine does that).
>
> Note that this commit include the ricv_array which embeds cpus. There

Typo "includes" I guess.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> are some deep internal constraints about them: you cannot create more
> cpus than the machine's maxcpus. TCG accelerator's code will for example
> assert if a user try to create too many cpus.
>
> Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
> ---
>
> I can also split this patch if you think it's better.
> But it is mostly a one-line fix per file.
>
> This patch requires first some cleanups in order to fix error errors
> and some more memory leaks that could happend in legit user-related
> life cycles: a miss-configuration should not be a fatal error anymore.
> https://lore.kernel.org/qemu-devel/20220218164646.132112-1-damien.hedde@greensocs.com
> ---
>   hw/char/ibex_uart.c     | 1 +
>   hw/char/sifive_uart.c   | 1 +
>   hw/gpio/sifive_gpio.c   | 1 +
>   hw/intc/riscv_aclint.c  | 2 ++
>   hw/intc/sifive_plic.c   | 1 +
>   hw/misc/sifive_e_prci.c | 8 ++++++++
>   hw/misc/unimp.c         | 1 +
>   hw/riscv/riscv_hart.c   | 1 +
>   hw/timer/ibex_timer.c   | 1 +
>   9 files changed, 17 insertions(+)