Re: [PATCH 2/2] target/riscv: Allow software access to MIP SEIP

[Bin Meng]

On Tue, Mar 15, 2022 at 2:40 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The RISC-V specification states that:
>   "Supervisor-level external interrupts are made pending based on the
>   logical-OR of the software-writable SEIP bit and the signal from the
>   external interrupt controller."
>
> We currently only allow either the interrupt controller or software to
> set the bit, which is incorrect.
>
> This patch removes the miclaim mask when writing MIP to allow M-mode
> software to inject interrupts, even with an interrupt controller.
>
> We then also need to keep track of which source is setting MIP_SEIP. The
> final value is a OR of both, so we add two bools and use that to keep
> track of the current state. This way either source can change without
> loosing the correct value.

losing?

>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/904
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu.h |  8 ++++++++
>  target/riscv/cpu.c | 10 +++++++++-
>  target/riscv/csr.c |  8 ++++++--
>  3 files changed, 23 insertions(+), 3 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>