Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl

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Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl

From:	Weiwei Li
Subject:	Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl
Date:	Sat, 19 Mar 2022 21:56:04 +0800
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0


在 2022/3/12 下午2:28, ~eopxd 写道:

From: eopXD <eop.chen@sifive.com>

According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
  target/riscv/insn_trans/trans_rvv.c.inc | 30 +++++++++++++++++++++++++
  1 file changed, 30 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 275fded6e4..3ae75dc6ae 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -652,6 +652,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, 
uint32_t data,

TCGLabel *over = gen_new_label();

      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

      mask = tcg_temp_new_ptr();
@@ -818,6 +819,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, 
uint32_t rs2,

TCGLabel *over = gen_new_label();

      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

      mask = tcg_temp_new_ptr();
@@ -925,6 +927,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, 
uint32_t vs2,

TCGLabel *over = gen_new_label();

      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

      mask = tcg_temp_new_ptr();
@@ -1067,6 +1070,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, 
uint32_t data,

TCGLabel *over = gen_new_label();

      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

      mask = tcg_temp_new_ptr();
@@ -1216,6 +1220,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn 
*gvec_fn,
      }

tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);

+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

if (a->vm && s->vl_eq_vlmax) {

          gvec_fn(s->sew, vreg_ofs(s, a->rd),
@@ -1263,6 +1268,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, 
uint32_t vs2, uint32_t vm,

TCGLabel *over = gen_new_label();

      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

      mask = tcg_temp_new_ptr();
@@ -1427,6 +1433,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, 
uint32_t vs2, uint32_t vm,

TCGLabel *over = gen_new_label();

      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

      mask = tcg_temp_new_ptr();
@@ -1513,6 +1520,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

data = FIELD_DP32(data, VDATA, VM, a->vm);

          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -1593,6 +1601,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

data = FIELD_DP32(data, VDATA, VM, a->vm);

          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -1670,6 +1679,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
         \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -1851,6 +1861,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
         \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -2061,6 +2072,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
              };
              TCGLabel *over = gen_new_label();
              tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),

                                 cpu_env, s->cfg_ptr->vlen / 8,
@@ -2084,6 +2096,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
          TCGv s1;
          TCGLabel *over = gen_new_label();
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

s1 = get_gpr(s, a->rs1, EXT_SIGN);@@ -2139,6 +2152,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)

              };
              TCGLabel *over = gen_new_label();
              tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+            tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

s1 = tcg_constant_i64(simm);

              dest = tcg_temp_new_ptr();
@@ -2291,6 +2305,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
         \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm(s, RISCV_FRM_DYN);                              \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -2321,6 +2336,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, 
uint32_t vs2,

TCGLabel *over = gen_new_label();

      tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

      mask = tcg_temp_new_ptr();
@@ -2409,6 +2425,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
       \
          TCGLabel *over = gen_new_label();                        \
          gen_set_rm(s, RISCV_FRM_DYN);                            \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);        \
+        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\


Maybe miss a space here.

Regards,

Weiwei Li

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[PATCH qemu 00/13] Add tail agnostic behavior for rvv instructions, ~eopxd, 2022/03/19
- [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl, ~eopxd, 2022/03/19
  - Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl, Weiwei Li <=
  - Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl, Weiwei Li, 2022/03/20
- [PATCH qemu 01/13] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, ~eopxd, 2022/03/19
  - Re: [PATCH qemu 01/13] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, Weiwei Li, 2022/03/19
- [PATCH qemu 04/13] target/riscv: rvv: Add tail agnostic for vv instructions, ~eopxd, 2022/03/19
  - Re: [PATCH qemu 04/13] target/riscv: rvv: Add tail agnostic for vv instructions, Weiwei Li, 2022/03/19
- [PATCH qemu 05/13] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, ~eopxd, 2022/03/19
  - Re: [PATCH qemu 05/13] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, Weiwei Li, 2022/03/19
- [PATCH qemu 07/13] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, ~eopxd, 2022/03/19
  - Re: [PATCH qemu 07/13] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, Weiwei Li, 2022/03/19
- [PATCH qemu 06/13] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, ~eopxd, 2022/03/19

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