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[RFC PATCH v1 0/4] RISC-V Smstateen support
From: |
Mayuresh Chitale |
Subject: |
[RFC PATCH v1 0/4] RISC-V Smstateen support |
Date: |
Tue, 22 Mar 2022 19:12:14 +0530 |
This series adds support for the Smstateen specification which provides
a mechanism plug potential covert channels which are opened by extensions
that add to processor state that may not get context-switched. Currently
access to AIA registers, *envcfg registers and floating point(fcsr) is
controlled via smstateen.
This series depends on the following series from Atish Patra:
https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00031.html
https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00142.html
Mayuresh Chitale (4):
target/riscv: Add smstateen support
target/riscv: smstateen check for h/senvcfg
target/riscv: smstateen check for fcsr
target/riscv: smstateen check for AIA/IMSIC
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 4 +
target/riscv/cpu_bits.h | 36 +++
target/riscv/csr.c | 550 +++++++++++++++++++++++++++++++++++++++-
target/riscv/machine.c | 22 +-
5 files changed, 610 insertions(+), 4 deletions(-)
--
2.17.1
- [RFC PATCH v1 0/4] RISC-V Smstateen support,
Mayuresh Chitale <=