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From: | eop Chen |
Subject: | Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions |
Date: | Wed, 30 Mar 2022 18:02:57 +0800 |
According to v-spec (under section 7.8):
I think the spec has explained itself that NFIELDS represents the number of register groups involved in this instruction. Therefore in a register group of 4 (LMUL = m2), NFIELD should be no more than 2. The `vlmax` here would be (VLEN * 4 / EEW). In this sense, if the `vl` provided for the vector instruction is within the range 2 * vlmax / 4 <= vl <= 3 * vlmax / 4, the elements in the 4th register (namely reg+3) will all be counted as tail elements. I hope this answers your question. Regards, eop Chen |
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