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[RFC PATCH 11/18] hw/riscv: prepare riscv_hart transition to cpus
From: |
Damien Hedde |
Subject: |
[RFC PATCH 11/18] hw/riscv: prepare riscv_hart transition to cpus |
Date: |
Wed, 30 Mar 2022 14:56:32 +0200 |
+ Use riscv_array_get_hart instead of accessing harts field.
+ Use riscv_hart_array_realize instead of sysbus_realize.
spike and virt machines will be handled separately in following
commits.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
---
hw/riscv/boot.c | 2 +-
hw/riscv/microchip_pfsoc.c | 4 ++--
hw/riscv/opentitan.c | 2 +-
hw/riscv/shakti_c.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 8 ++++----
6 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index cae74fcbcd..b21c8f6488 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -36,7 +36,7 @@
bool riscv_is_32bit(RISCVHartArrayState *harts)
{
- return harts->harts[0].env.misa_mxl_max == MXL_RV32;
+ return riscv_array_get_hart(harts, 0)->env.misa_mxl_max == MXL_RV32;
}
/*
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index cafd1fc9ae..82547a53e6 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -190,8 +190,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
NICInfo *nd;
int i;
- sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
+ riscv_hart_array_realize(&s->e_cpus, &error_abort);
+ riscv_hart_array_realize(&s->u_cpus, &error_abort);
/*
* The cluster must be realized after the RISC-V hart array container,
* as the container's CPU object is only created on realize, and the
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 833624d66c..2eb7454d8a 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -135,7 +135,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc,
Error **errp)
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080,
&error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+ riscv_hart_array_realize(&s->cpus, &error_abort);
/* Boot ROM */
memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 90e2cf609f..93e0c8dd68 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -108,7 +108,7 @@ static void shakti_c_soc_state_realize(DeviceState *dev,
Error **errp)
ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
MemoryRegion *system_memory = get_system_memory();
- sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
+ riscv_hart_array_realize(&sss->cpus, &error_abort);
sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
(char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0,
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index dcb87b6cfd..25ba0a8c85 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -195,7 +195,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error
**errp)
object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
&error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+ riscv_hart_array_realize(&s->cpus, &error_abort);
/* Mask ROM */
memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7fbc7dea42..c99e92a7eb 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -188,9 +188,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
*memmap,
} else {
qemu_fdt_setprop_string(fdt, nodename, "mmu-type",
"riscv,sv48");
}
- isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
+ isa = riscv_isa_string(riscv_array_get_hart(&s->soc.u_cpus, cpu -
1));
} else {
- isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
+ isa = riscv_isa_string(riscv_array_get_hart(&s->soc.e_cpus, 0));
}
qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
@@ -830,8 +830,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error
**errp)
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
- sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
+ riscv_hart_array_realize(&s->e_cpus, &error_abort);
+ riscv_hart_array_realize(&s->u_cpus, &error_abort);
/*
* The cluster must be realized after the RISC-V hart array container,
* as the container's CPU object is only created on realize, and the
--
2.35.1
- [RFC PATCH 00/18] user-creatable cpu clusters, Damien Hedde, 2022/03/30
- [RFC PATCH 01/18] define MAX_CLUSTERS in cpu.h instead of cluster.h, Damien Hedde, 2022/03/30
- [RFC PATCH 03/18] hw/cpu/cpus: prepare to handle cpu clusters, Damien Hedde, 2022/03/30
- [RFC PATCH 02/18] hw/cpu/cpus: introduce _cpus_ device, Damien Hedde, 2022/03/30
- [RFC PATCH 04/18] hw/cpu/cluster: make _cpu-cluster_ a subclass of _cpus_, Damien Hedde, 2022/03/30
- [RFC PATCH 05/18] gdbstub: deal with _cpus_ object instead of _cpu-cluster_, Damien Hedde, 2022/03/30
- [RFC PATCH 06/18] hw/cpu/cluster: remove cluster_id now that gdbstub is updated, Damien Hedde, 2022/03/30
- [RFC PATCH 09/18] hw/arm/xlnx-zynqmp: convert cpu clusters to arm_cpus, Damien Hedde, 2022/03/30
- [RFC PATCH 08/18] hw/arm/arm_cpus: add arm_cpus device, Damien Hedde, 2022/03/30
- [RFC PATCH 07/18] hw/cpu/cpus: add a common start-powered-off property, Damien Hedde, 2022/03/30
- [RFC PATCH 11/18] hw/riscv: prepare riscv_hart transition to cpus,
Damien Hedde <=
- [RFC PATCH 13/18] hw/riscv/spike: prepare riscv_hart transition to cpus, Damien Hedde, 2022/03/30
- [RFC PATCH 10/18] hw/riscv/riscv_hart: prepare transition to cpus, Damien Hedde, 2022/03/30
- [RFC PATCH 15/18] hw/riscv/sifive_uµchip_pfsoc: apply riscv_hart_array update, Damien Hedde, 2022/03/30
- [RFC PATCH 17/18] hw/riscv/riscv_hart: remove temporary features, Damien Hedde, 2022/03/30
- [RFC PATCH 14/18] hw/riscv/riscv_hart: use cpus as base class, Damien Hedde, 2022/03/30
- [RFC PATCH 16/18] hw/riscv: update remaining machines due to riscv_hart_array update, Damien Hedde, 2022/03/30
- [RFC PATCH 18/18] add myself as reviewer of the newly added _cpus_, Damien Hedde, 2022/03/30
- [RFC PATCH 12/18] hw/riscv/virt: prepare riscv_hart transition to cpus, Damien Hedde, 2022/03/30