[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v3 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write access
From: |
frank . chang |
Subject: |
[PATCH v3 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses |
Date: |
Tue, 19 Apr 2022 17:08:41 +0800 |
From: Frank Chang <frank.chang@sifive.com>
This patchset makes ACLINT mtime to be writable as RISC-V privilege
spec defines that mtime is exposed as a memory-mapped machine-mode
read-write register. Also, mtimecmp and mtime should be 32/64-bit memory
accessible registers. ACLINT reset function is also added, which requires
mtime to be resetable if we need to support core power-gating feature in
the future.
This patchset is the updated verion of:
https://patchew.org/QEMU/20220126095448.2964-1-frank.chang@sifive.com/
Changelog:
v3:
* Forbid 8-byte write access to timecmp_hi and time_hi.
* Add ACLINT reset function.
v2:
* Support 32/64-bit mtimecmp/mtime memory accesses.
* Add .impl.[min|max]_access_size declaration.
Frank Chang (3):
hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V
ACLINT
hw/intc: Make RISC-V ACLINT mtime MMIO register writable
Jim Shu (1):
hw/intc: riscv_aclint: Add reset function of ACLINT devices
hw/intc/riscv_aclint.c | 144 ++++++++++++++++++++++++++-------
include/hw/intc/riscv_aclint.h | 1 +
target/riscv/cpu.h | 8 +-
target/riscv/cpu_helper.c | 4 +-
4 files changed, 121 insertions(+), 36 deletions(-)
--
2.35.1
- [PATCH v3 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses,
frank . chang <=