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Re: [PATCH 1/4] target/riscv: Fix csr number based privilege checking
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH 1/4] target/riscv: Fix csr number based privilege checking |
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Date: |
Fri, 29 Apr 2022 20:54:54 +1000 |
On Fri, Apr 29, 2022 at 1:36 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
> the riscv_csrrw_check() function should generate virtual instruction
> trap instead illegal instruction trap.
>
> Fixes: 533c91e8f22c ("target/riscv: Use RISCVException enum for
> CSR access")
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 3500e07f92..2bf0a97196 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3139,7 +3139,7 @@ static inline RISCVException
> riscv_csrrw_check(CPURISCVState *env,
> int read_only = get_field(csrno, 0xC00) == 3;
> int csr_min_priv = csr_ops[csrno].min_priv_ver;
> #if !defined(CONFIG_USER_ONLY)
> - int effective_priv = env->priv;
> + int csr_priv, effective_priv = env->priv;
>
> if (riscv_has_ext(env, RVH) &&
> env->priv == PRV_S &&
> @@ -3152,7 +3152,11 @@ static inline RISCVException
> riscv_csrrw_check(CPURISCVState *env,
> effective_priv++;
> }
>
> - if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
> + csr_priv = get_field(csrno, 0x300);
> + if (!env->debugger && (effective_priv < csr_priv)) {
> + if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) {
> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> + }
> return RISCV_EXCP_ILLEGAL_INST;
> }
> #endif
> --
> 2.34.1
>
>