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[PATCH v2 1/8] target/riscv: Fix csr number based privilege checking
From: |
Anup Patel |
Subject: |
[PATCH v2 1/8] target/riscv: Fix csr number based privilege checking |
Date: |
Wed, 11 May 2022 20:15:21 +0530 |
When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
the riscv_csrrw_check() function should generate virtual instruction
trap instead illegal instruction trap.
Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/csr.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3500e07f92..2bf0a97196 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3139,7 +3139,7 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
int read_only = get_field(csrno, 0xC00) == 3;
int csr_min_priv = csr_ops[csrno].min_priv_ver;
#if !defined(CONFIG_USER_ONLY)
- int effective_priv = env->priv;
+ int csr_priv, effective_priv = env->priv;
if (riscv_has_ext(env, RVH) &&
env->priv == PRV_S &&
@@ -3152,7 +3152,11 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
effective_priv++;
}
- if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
+ csr_priv = get_field(csrno, 0x300);
+ if (!env->debugger && (effective_priv < csr_priv)) {
+ if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
--
2.34.1
- [PATCH v2 0/8] QEMU RISC-V nested virtualization fixes, Anup Patel, 2022/05/11
- [PATCH v2 1/8] target/riscv: Fix csr number based privilege checking,
Anup Patel <=
- [PATCH v2 2/8] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode, Anup Patel, 2022/05/11
- [PATCH v2 3/8] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps, Anup Patel, 2022/05/11
- [PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt(), Anup Patel, 2022/05/11
- [PATCH v2 5/8] target/riscv: Don't force update priv spec version to latest, Anup Patel, 2022/05/11
- [PATCH v2 6/8] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher, Anup Patel, 2022/05/11