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[PATCH qemu v17 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to
From: |
~eopxd |
Subject: |
[PATCH qemu v17 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior |
Date: |
Wed, 27 Apr 2022 20:26:40 -0700 |
From: eopXD <eop.chen@sifive.com>
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between tail policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This commit adds option 'rvv_ta_all_1s' is added to enable the
behavior, it is default as disabled.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ccacdee215..720c8b9e5c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -879,6 +879,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+ DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.2
- [PATCH qemu v17 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions, (continued)
- [PATCH qemu v17 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 03/16] target/riscv: rvv: Rename ambiguous esz, ~eopxd, 2022/05/12
- [PATCH qemu v17 08/16] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 09/16] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 07/16] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 01/16] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, ~eopxd, 2022/05/12
- [PATCH qemu v17 02/16] target/riscv: rvv: Prune redundant access_type parameter passed, ~eopxd, 2022/05/12
- [PATCH qemu v17 15/16] target/riscv: rvv: Add tail agnostic for vector permutation instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 12/16] target/riscv: rvv: Add tail agnostic for vector floating-point instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 14/16] target/riscv: rvv: Add tail agnostic for vector mask instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior,
~eopxd <=
- [PATCH qemu v17 10/16] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 13/16] target/riscv: rvv: Add tail agnostic for vector reduction instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 11/16] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/05/12