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Re: [PATCH v3 1/4] dt-bindings: timer: sifive,clint: add legacy riscv co
From: |
Rob Herring |
Subject: |
Re: [PATCH v3 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible |
Date: |
Thu, 18 Aug 2022 10:36:26 -0600 |
On Wed, Aug 17, 2022 at 09:12:10PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> While "real" hardware might not use the compatible string "riscv,clint0"
> it is present in the driver & QEMU uses it for automatically generated
> virt machine dtbs. To avoid dt-validate problems with QEMU produced
> dtbs, such as the following, add it to the binding.
>
> riscv-virt.dtb: clint@2000000: compatible:0: 'sifive,clint0' is not one of
> ['sifive,fu540-c000-clint', 'starfive,jh7100-clint', 'canaan,k210-clint']
>
> Reported-by: Rob Herring <robh@kernel.org>
> Link:
> https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/timer/sifive,clint.yaml | 18 ++++++++++++------
> 1 file changed, 12 insertions(+), 6 deletions(-)
Reviewed-by: Rob Herring <robh@kernel.org>
- [PATCH v3 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings, Conor Dooley, 2022/08/17
- [PATCH v3 1/4] dt-bindings: timer: sifive, clint: add legacy riscv compatible, Conor Dooley, 2022/08/17
- Re: [PATCH v3 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible,
Rob Herring <=
- [PATCH v3 2/4] dt-bindings: interrupt-controller: sifive, plic: add legacy riscv compatible, Conor Dooley, 2022/08/17
- [PATCH v3 3/4] dt-bindings: riscv: add new riscv, isa strings for emulators, Conor Dooley, 2022/08/17
- [NOT FOR INCLUSION v3 4/4] dt-bindings: riscv: isa string bonus content, Conor Dooley, 2022/08/17