Re: [RFC PATCH 3/3] tcg/riscv: Remove a wrong optimization for addsub2

[Richard Henderson]

On 10/20/22 20:41, LIU Zhiwei wrote:
> It's not clear what it is doing here. And it's wrong because bl and
> al are both register, so we can't add them by an ADDI instruction.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
>   tcg/riscv/tcg-target.c.inc | 3 ---
>   1 file changed, 3 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index bfdf2bea69..a07fd0864f 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -705,9 +705,6 @@ static void tcg_out_addsub2(TCGContext *s,
>                   tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
>                                   rl, al);
>               }
> -        } else if (rl == al && rl == bl) {
> -            tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
> -            tcg_out_opc_reg(s, opc_addi, rl, al, bl);
>           } else {

Removing this is incorrect; it's a simple typo for opc_add.

The case being required for rl == al == bl, which the following else will treat 
incorrectly.


r~