Re: [PATCH v5 3/9] target/riscv: add support for Zcf extension

[Alistair Francis]

On Fri, Nov 18, 2022 at 10:44 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn16.decode              |  8 ++++----
>  target/riscv/insn_trans/trans_rvf.c.inc | 18 ++++++++++++++++++
>  2 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index ccfe59f294..f3ea650325 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -109,11 +109,11 @@ sw                110  ... ... .. ... 00 @cs_w
>  # *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
>  {
>    ld              011  ... ... .. ... 00 @cl_d
> -  flw             011  ... ... .. ... 00 @cl_w
> +  c_flw           011  ... ... .. ... 00 @cl_w
>  }
>  {
>    sd              111  ... ... .. ... 00 @cs_d
> -  fsw             111  ... ... .. ... 00 @cs_w
> +  c_fsw           111  ... ... .. ... 00 @cs_w
>  }
>
>  # *** RV32/64C Standard Extension (Quadrant 1) ***
> @@ -174,9 +174,9 @@ sw                110 .  .....  ..... 10 @c_swsp
>  {
>    c64_illegal     011 -  00000  ----- 10 # c.ldsp, RES rd=0
>    ld              011 .  .....  ..... 10 @c_ldsp
> -  flw             011 .  .....  ..... 10 @c_lwsp
> +  c_flw           011 .  .....  ..... 10 @c_lwsp
>  }
>  {
>    sd              111 .  .....  ..... 10 @c_sdsp
> -  fsw             111 .  .....  ..... 10 @c_swsp
> +  c_fsw           111 .  .....  ..... 10 @c_swsp
>  }
> diff --git a/target/riscv/insn_trans/trans_rvf.c.inc 
> b/target/riscv/insn_trans/trans_rvf.c.inc
> index 93657680c6..426518957b 100644
> --- a/target/riscv/insn_trans/trans_rvf.c.inc
> +++ b/target/riscv/insn_trans/trans_rvf.c.inc
> @@ -24,6 +24,12 @@
>              return false; \
>  } while (0)
>
> +#define REQUIRE_ZCF(ctx) do {                  \
> +    if (!ctx->cfg_ptr->ext_zcf) {              \
> +        return false;                          \
> +    }                                          \
> +} while (0)
> +
>  #ifndef CONFIG_USER_ONLY
>  static inline bool smstateen_fcsr_check(DisasContext *ctx, int index)
>  {
> @@ -96,6 +102,18 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
>      return true;
>  }
>
> +static bool trans_c_flw(DisasContext *ctx, arg_flw *a)
> +{
> +    REQUIRE_ZCF(ctx);
> +    return trans_flw(ctx, a);
> +}
> +
> +static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a)
> +{
> +    REQUIRE_ZCF(ctx);
> +    return trans_fsw(ctx, a);
> +}
> +
>  static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
>  {
>      REQUIRE_FPU;
> --
> 2.25.1
>
>