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Re: [PATCH 11/15] hw/riscv: sifive_u: Avoid using magic number for "risc
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH 11/15] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" |
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Date: |
Wed, 7 Dec 2022 14:33:53 +1000 |
On Fri, Dec 2, 2022 at 12:11 AM Bin Meng <bmeng@tinylab.org> wrote:
>
> At present magic number is used to create "riscv,ndev" property
> in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
> is used to instantiate the PLIC model instead.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index b139824aab..b40a4767e2 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -287,7 +287,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
> *memmap,
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
> 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
> - qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
> + qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
> + SIFIVE_U_PLIC_NUM_SOURCES - 1);
> qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
> plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
> g_free(cells);
> --
> 2.34.1
>
>
- [PATCH 04/15] hw/riscv: Sort machines Kconfig options in alphabetical order, (continued)
- [PATCH 04/15] hw/riscv: Sort machines Kconfig options in alphabetical order, Bin Meng, 2022/12/01
- [PATCH 08/15] hw/intc: sifive_plic: Update "num-sources" property default value, Bin Meng, 2022/12/01
- [PATCH 09/15] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/01
- [PATCH 11/15] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", Bin Meng, 2022/12/01
- [PATCH 10/15] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/01
- [PATCH 12/15] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Bin Meng, 2022/12/01
- [PATCH 13/15] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Bin Meng, 2022/12/01
- [PATCH 14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization, Bin Meng, 2022/12/01