[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 01/15] tests/avocado: add RISC-V opensbi boot test
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH 01/15] tests/avocado: add RISC-V opensbi boot test |
Date: |
Wed, 21 Dec 2022 15:22:46 -0300 |
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.
'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
RISCV32_BIOS_BIN firmware with minimal options.
Cc: Cleber Rosa <crosa@redhat.com>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Wainer dos Santos Moschetta <wainersm@redhat.com>
Cc: Beraldo Leal <bleal@redhat.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 tests/avocado/riscv_opensbi.py
diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py
new file mode 100644
index 0000000000..abc99ced30
--- /dev/null
+++ b/tests/avocado/riscv_opensbi.py
@@ -0,0 +1,65 @@
+# opensbi boot test for RISC-V machines
+#
+# Copyright (c) 2022, Ventana Micro
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+from avocado_qemu import QemuSystemTest
+from avocado_qemu import wait_for_console_pattern
+
+class RiscvOpensbi(QemuSystemTest):
+ """
+ :avocado: tags=accel:tcg
+ """
+ timeout = 5
+
+ def test_riscv64_virt(self):
+ """
+ :avocado: tags=arch:riscv64
+ :avocado: tags=machine:virt
+ """
+ self.vm.set_console()
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Platform Name')
+ wait_for_console_pattern(self, 'Boot HART MEDELEG')
+
+ def test_riscv64_spike(self):
+ """
+ :avocado: tags=arch:riscv64
+ :avocado: tags=machine:spike
+ """
+ self.vm.set_console()
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Platform Name')
+ wait_for_console_pattern(self, 'Boot HART MEDELEG')
+
+ def test_riscv64_sifive_u(self):
+ """
+ :avocado: tags=arch:riscv64
+ :avocado: tags=machine:sifive_u
+ """
+ self.vm.set_console()
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Platform Name')
+ wait_for_console_pattern(self, 'Boot HART MEDELEG')
+
+ def test_riscv32_virt(self):
+ """
+ :avocado: tags=arch:riscv32
+ :avocado: tags=machine:virt
+ """
+ self.vm.set_console()
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Platform Name')
+ wait_for_console_pattern(self, 'Boot HART MEDELEG')
+
+ def test_riscv32_sifive_u(self):
+ """
+ :avocado: tags=arch:riscv32
+ :avocado: tags=machine:sifive_u
+ """
+ self.vm.set_console()
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Platform Name')
+ wait_for_console_pattern(self, 'Boot HART MEDELEG')
--
2.38.1
- [PATCH 00/15] riscv: opensbi boot test and cleanups, Daniel Henrique Barboza, 2022/12/21
- [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test,
Daniel Henrique Barboza <=
- Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test, Bin Meng, 2022/12/22
- Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test, Daniel Henrique Barboza, 2022/12/22
- Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test, Bin Meng, 2022/12/22
- Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test, Anup Patel, 2022/12/22
- Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test, Daniel Henrique Barboza, 2022/12/22
- Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test, Bin Meng, 2022/12/23
- Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test, Bin Meng, 2022/12/23
- Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test, Bin Meng, 2022/12/26
- Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test, Daniel Henrique Barboza, 2022/12/26
- Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test, Daniel Henrique Barboza, 2022/12/27