[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v4 01/11] tests/avocado: add RISC-V OpenSBI boot test

From: Philippe Mathieu-Daudé
Subject: Re: [PATCH v4 01/11] tests/avocado: add RISC-V OpenSBI boot test
Date: Fri, 30 Dec 2022 13:50:59 +0100
User-agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1

On 29/12/22 19:11, Daniel Henrique Barboza wrote:
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.

'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
RISCV32_BIOS_BIN firmware with minimal options.

The riscv32 'spike' machine isn't bootable at this moment, requiring an
OpenSBI fix [1] and QEMU side changes [2]. We could just leave at that
or add a 'skip' test to remind us about it. To work as a reminder that
we have a riscv32 'spike' test that should be enabled as soon as OpenSBI
QEMU rom receives the fix, we're adding a 'skip' test:

(06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike:
         SKIP: requires OpenSBI fix to work

[2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159

Cc: Cleber Rosa <crosa@redhat.com>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Tested-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++
  1 file changed, 65 insertions(+)
  create mode 100644 tests/avocado/riscv_opensbi.py

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

reply via email to

[Prev in Thread] Current Thread [Next in Thread]