Re: [PATCH v7 0/4] riscv: Add support for Zicbo[m,z,p] instructions

[Daniel Henrique Barboza]

Hi Palmer,

On 3/1/23 18:35, Palmer Dabbelt wrote:
> On Thu, 23 Feb 2023 15:44:23 PST (-0800), dbarboza@ventanamicro.com wrote:
> > Hi,
> >
> > This new version has changes based on feedbacks of both v5 and v6.
> >
> > Patch 1 was revamped. We're modifying probe_access_flags() to accept a
> > 'size' parameter to allow for RISC-V usage with PMP. Changes in the existing
> > callers are trivial and no behavior change is done (well, at least it's not
> > intended). And we avoid adding another  probe_* API that only RISC-V
> > will care about.
> >
> > Changes from v6:
> > - patch 1:
> >   - no longer adding a new probe_access_flags_range() API
> >   - add a 'size' param to probe_access_flags()
> > - patch 2:
> >   - check for RISCV_EXCP_ILLEGAL_INST first in check_zicbo_envcfg()
> >   - add a probe for MMU_DATA_STORE after check_zicbo_envcfg()
> >   - write zeros even if the address isn't mapped to RAM
> > - patch 3:
> >   - simplify the verifications in check_zicbom_access() by using probe_write()
> > - v6 link: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg05379.html
> >
> > Christoph Muellner (3):
> >   target/riscv: implement Zicboz extension
> >   target/riscv: implement Zicbom extension
> >   target/riscv: add Zicbop cbo.prefetch{i,r,m} placeholder
> >
> > Daniel Henrique Barboza (1):
> >   tcg: add 'size' param to probe_access_flags()
> >
> >  accel/stubs/tcg-stub.c                      |   2 +-
> >  accel/tcg/cputlb.c                          |  17 ++-
> >  accel/tcg/user-exec.c                       |   5 +-
> >  include/exec/exec-all.h                     |   3 +-
> >  semihosting/uaccess.c                       |   2 +-
> >  target/arm/ptw.c                            |   2 +-
> >  target/arm/sve_helper.c                     |   2 +-
> >  target/riscv/cpu.c                          |   7 ++
> >  target/riscv/cpu.h                          |   4 +
> >  target/riscv/helper.h                       |   5 +
> >  target/riscv/insn32.decode                  |  16 ++-
> >  target/riscv/insn_trans/trans_rvzicbo.c.inc |  57 +++++++++
> >  target/riscv/op_helper.c                    | 132 ++++++++++++++++++++
> >  target/riscv/translate.c                    |   1 +
> >  target/s390x/tcg/mem_helper.c               |   6 +-
> >  15 files changed, 247 insertions(+), 14 deletions(-)
> >  create mode 100644 target/riscv/insn_trans/trans_rvzicbo.c.inc
>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>


Thanks! I guess you would want to pick the new version instead that is already
fully acked:

[PATCH v8 0/4] riscv: Add support for Zicbo[m,z,p] instructions


Richard already picked and sent patch 1 in his tcg patch queue here:


[PULL v2 00/62] tcg patch queue

So I guess you can either include patch 1 in your tree and exclude it when 
master
is updated or you can wait for patch 1 to land on master before picking the 
remaining
3 patches.


Thanks,


Daniel


> in case Richard wants to take these along with the TCG patch, otherwise I'm 
> happy to take these through the RISC-V tree when that lands (or do some sort of 
> shared tag, as we're getting kind of close).