Re: [PATCH] RISC-V: XTheadMemPair: Remove register restrictions for store-pair

[Palmer Dabbelt]

On Mon, 20 Feb 2023 01:56:12 PST (-0800), christoph.muellner@vrull.eu wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> The XTheadMemPair does not define any restrictions for store-pair
> instructions (th.sdd or th.swd). However, the current code enforces
> the restrictions that are required for load-pair instructions.
> Let's fix this by removing this code.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  target/riscv/insn_trans/trans_xthead.c.inc | 4 ----
>  1 file changed, 4 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc 
> b/target/riscv/insn_trans/trans_xthead.c.inc
> index be87c34f56..cf1731b08d 100644
> --- a/target/riscv/insn_trans/trans_xthead.c.inc
> +++ b/target/riscv/insn_trans/trans_xthead.c.inc
> @@ -980,10 +980,6 @@ static bool trans_th_lwud(DisasContext *ctx, arg_th_pair 
> *a)
>  static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
>                               int shamt)
>  {
> -    if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
> -        return false;
> -    }
> -
>      TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
>      TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
>      TCGv addr1 = tcg_temp_new();

Thanks, this is queued in riscv-to-apply.next .