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[PULL 44/59] RISC-V: XTheadMemPair: Remove register restrictions for sto
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From: |
Palmer Dabbelt |
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Subject: |
[PULL 44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair |
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Date: |
Fri, 3 Mar 2023 00:37:25 -0800 |
From: Christoph Müllner <christoph.muellner@vrull.eu>
The XTheadMemPair does not define any restrictions for store-pair
instructions (th.sdd or th.swd). However, the current code enforces
the restrictions that are required for load-pair instructions.
Let's fix this by removing this code.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230220095612.1529031-1-christoph.muellner@vrull.eu>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/insn_trans/trans_xthead.c.inc | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc
b/target/riscv/insn_trans/trans_xthead.c.inc
index be87c34f56..cf1731b08d 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -980,10 +980,6 @@ static bool trans_th_lwud(DisasContext *ctx, arg_th_pair
*a)
static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
int shamt)
{
- if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
- return false;
- }
-
TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
TCGv addr1 = tcg_temp_new();
--
2.39.2
- [PULL 29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled, (continued)
- [PULL 29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled, Palmer Dabbelt, 2023/03/03
- [PULL 31/59] target/riscv: Use 'bool' type for read_only, Palmer Dabbelt, 2023/03/03
- [PULL 32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit, Palmer Dabbelt, 2023/03/03
- [PULL 33/59] target/riscv: Simplify getting RISCVCPU pointer from env, Palmer Dabbelt, 2023/03/03
- [PULL 34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64, Palmer Dabbelt, 2023/03/03
- [PULL 30/59] target/riscv: Coding style fixes in csr.c, Palmer Dabbelt, 2023/03/03
- [PULL 35/59] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate(), Palmer Dabbelt, 2023/03/03
- [PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml, Palmer Dabbelt, 2023/03/03
- [PULL 39/59] target/riscv: Allow debugger to access {h, s}stateen CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 43/59] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages, Palmer Dabbelt, 2023/03/03
- [PULL 44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair,
Palmer Dabbelt <=
- [PULL 38/59] target/riscv: Allow debugger to access seed CSR, Palmer Dabbelt, 2023/03/03
- [PULL 37/59] target/riscv: Allow debugger to access user timer and counter CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 46/59] hw/riscv: Skip re-generating DT nodes for a given DTB, Palmer Dabbelt, 2023/03/03
- [PULL 40/59] target/riscv: Allow debugger to access sstc CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 41/59] target/riscv: Drop priv level check in mseccfg predicate(), Palmer Dabbelt, 2023/03/03
- [PULL 42/59] target/riscv: Group all predicate() routines together, Palmer Dabbelt, 2023/03/03
- [PULL 48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions, Palmer Dabbelt, 2023/03/03
- [PULL 45/59] target/riscv: Add support for Zicond extension, Palmer Dabbelt, 2023/03/03
- [PULL 55/59] target/riscv/csr.c: simplify mctr(), Palmer Dabbelt, 2023/03/03
- [PULL 47/59] hw/riscv: Move the dtb load bits outside of create_fdt(), Palmer Dabbelt, 2023/03/03