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[PULL 53/59] target/riscv: Export Svadu property
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From: |
Palmer Dabbelt |
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Subject: |
[PULL 53/59] target/riscv: Export Svadu property |
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Date: |
Fri, 3 Mar 2023 00:37:34 -0800 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Set it default true for backward compatibility
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-7-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 32cb297cfe..1be9f3f836 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -107,6 +107,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia),
ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc),
+ ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu),
ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
@@ -1104,6 +1105,8 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
+
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
--
2.39.2
- [PULL 41/59] target/riscv: Drop priv level check in mseccfg predicate(), (continued)
- [PULL 41/59] target/riscv: Drop priv level check in mseccfg predicate(), Palmer Dabbelt, 2023/03/03
- [PULL 42/59] target/riscv: Group all predicate() routines together, Palmer Dabbelt, 2023/03/03
- [PULL 48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions, Palmer Dabbelt, 2023/03/03
- [PULL 45/59] target/riscv: Add support for Zicond extension, Palmer Dabbelt, 2023/03/03
- [PULL 55/59] target/riscv/csr.c: simplify mctr(), Palmer Dabbelt, 2023/03/03
- [PULL 47/59] hw/riscv: Move the dtb load bits outside of create_fdt(), Palmer Dabbelt, 2023/03/03
- [PULL 49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg, Palmer Dabbelt, 2023/03/03
- [PULL 50/59] target/riscv: Add csr support for svadu, Palmer Dabbelt, 2023/03/03
- [PULL 51/59] target/riscv: Add *envcfg.PBMTE related check in address translation, Palmer Dabbelt, 2023/03/03
- [PULL 52/59] target/riscv: Add *envcfg.HADE related check in address translation, Palmer Dabbelt, 2023/03/03
- [PULL 53/59] target/riscv: Export Svadu property,
Palmer Dabbelt <=
- [PULL 57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig, Palmer Dabbelt, 2023/03/03
- [PULL 58/59] target/riscv/vector_helper.c: create vext_set_tail_elems_1s(), Palmer Dabbelt, 2023/03/03
- [PULL 56/59] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers, Palmer Dabbelt, 2023/03/03
- [PULL 54/59] target/riscv/csr.c: use env_archcpu() in ctr(), Palmer Dabbelt, 2023/03/03
- [PULL 59/59] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig, Palmer Dabbelt, 2023/03/03
- Re: [PULL 00/59] Fifth RISC-V PR for QEMU 8.0, Peter Maydell, 2023/03/03
- Re: [PULL 00/59] Fifth RISC-V PR for QEMU 8.0, Peter Maydell, 2023/03/03