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[PULL 05/22] disas/riscv Fix ctzw disassemble
From: |
Palmer Dabbelt |
Subject: |
[PULL 05/22] disas/riscv Fix ctzw disassemble |
Date: |
Mon, 6 Mar 2023 14:02:42 -0800 |
From: Ivan Klokov <ivan.klokov@syntacore.com>
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions")
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230217151459.54649-1-ivan.klokov@syntacore.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index ddda687c13..54455aaaa8 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1645,7 +1645,7 @@ const rv_opcode_data opcode_data[] = {
{ "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
--
2.39.2
- [PULL 00/22] Sixth RISC-V PR for 8.0, Palmer Dabbelt, 2023/03/06
- [PULL 01/22] target/riscv: implement Zicboz extension, Palmer Dabbelt, 2023/03/06
- [PULL 02/22] target/riscv: implement Zicbom extension, Palmer Dabbelt, 2023/03/06
- [PULL 05/22] disas/riscv Fix ctzw disassemble,
Palmer Dabbelt <=
- [PULL 03/22] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder, Palmer Dabbelt, 2023/03/06
- [PULL 04/22] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties, Palmer Dabbelt, 2023/03/06
- [PULL 06/22] target/riscv: cpu: Implement get_arch_id callback, Palmer Dabbelt, 2023/03/06
- [PULL 08/22] gitlab/opensbi: Move to docker:stable, Palmer Dabbelt, 2023/03/06
- [PULL 07/22] hw: intc: Use cpu_by_arch_id to fetch CPU state, Palmer Dabbelt, 2023/03/06
- [PULL 11/22] riscv: Change type of valid_vm_1_10_[32|64] to bool, Palmer Dabbelt, 2023/03/06
- [PULL 10/22] riscv: Pass Object to register_cpu_props instead of DeviceState, Palmer Dabbelt, 2023/03/06
- [PULL 12/22] riscv: Allow user to set the satp mode, Palmer Dabbelt, 2023/03/06
- [PULL 14/22] riscv: Correctly set the device-tree entry 'mmu-type', Palmer Dabbelt, 2023/03/06
- [PULL 13/22] riscv: Introduce satp mode hw capabilities, Palmer Dabbelt, 2023/03/06