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[PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loo
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From: |
Richard Henderson |
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Subject: |
[PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loop |
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Date: |
Sat, 25 Mar 2023 03:54:23 -0700 |
These values are constant for every level of pte lookup.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 833ea6d3fa..00f70a3dd5 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -870,6 +870,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
return TRANSLATE_FAIL;
}
+ bool pbmte = env->menvcfg & MENVCFG_PBMTE;
+ bool hade = env->menvcfg & MENVCFG_HADE;
+
+ if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
+ pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
+ hade = hade && (env->henvcfg & HENVCFG_HADE);
+ }
+
int ptshift = (levels - 1) * ptidxbits;
int i;
@@ -930,14 +938,6 @@ restart:
return TRANSLATE_FAIL;
}
- bool pbmte = env->menvcfg & MENVCFG_PBMTE;
- bool hade = env->menvcfg & MENVCFG_HADE;
-
- if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
- pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
- hade = hade && (env->henvcfg & HENVCFG_HADE);
- }
-
if (riscv_cpu_sxl(env) == MXL_RV32) {
ppn = pte >> PTE_PPN_SHIFT;
} else if (pbmte || cpu->cfg.ext_svnapot) {
--
2.34.1
- [PATCH v6 03/25] target/riscv: Encode the FS and VS on a normal way for tb flags, (continued)
- [PATCH v6 03/25] target/riscv: Encode the FS and VS on a normal way for tb flags, Richard Henderson, 2023/03/25
- [PATCH v6 10/25] target/riscv: Handle HLV, HSV via helpers, Richard Henderson, 2023/03/25
- [PATCH v6 22/25] target/riscv: Don't modify SUM with is_debug, Richard Henderson, 2023/03/25
- [PATCH v6 06/25] target/riscv: Separate priv from mmu_idx, Richard Henderson, 2023/03/25
- [PATCH v6 12/25] target/riscv: Introduce mmuidx_sum, Richard Henderson, 2023/03/25
- [PATCH v6 23/25] target/riscv: Merge checks for reserved pte flags, Richard Henderson, 2023/03/25
- [PATCH v6 20/25] target/riscv: Move leaf pte processing out of level loop, Richard Henderson, 2023/03/25
- [PATCH v6 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change, Richard Henderson, 2023/03/25
- [PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loop,
Richard Henderson <=
- [PATCH v6 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT, Richard Henderson, 2023/03/25
- [PATCH v6 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index, Richard Henderson, 2023/03/25
- [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv, Richard Henderson, 2023/03/25
- [PATCH v6 14/25] target/riscv: Introduce mmuidx_2stage, Richard Henderson, 2023/03/25
- [PATCH v6 21/25] target/riscv: Suppress pte update with is_debug, Richard Henderson, 2023/03/25
- [PATCH v6 17/25] target/riscv: Check SUM in the correct register, Richard Henderson, 2023/03/25
- [PATCH v6 01/25] target/riscv: Extract virt enabled state from tb flags, Richard Henderson, 2023/03/25