qemu-riscv
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v3 5/6] target/riscv: Enable PC-relative translation in syste


From: LIU Zhiwei
Subject: Re: [PATCH v3 5/6] target/riscv: Enable PC-relative translation in system mode
Date: Fri, 31 Mar 2023 15:59:16 +0800
User-agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1


On 2023/3/31 9:45, Weiwei Li wrote:
The existence of CF_PCREL can improve performance with the guest
kernel's address space randomization.  Each guest process maps
libc.so (et al) at a different virtual address, and this allows
those translations to be shared.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
  target/riscv/cpu.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 646fa31a59..3b562d5d9f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1193,6 +1193,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
**errp)
#ifndef CONFIG_USER_ONLY
+    cs->tcg_cflags |= CF_PCREL;
+

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei

      if (cpu->cfg.ext_sstc) {
          riscv_timer_init(cpu);
      }



reply via email to

[Prev in Thread] Current Thread [Next in Thread]